set link_library { /net/plato.ee.virginia.edu/users/sdb6t/Synopsys/mc/ref/tech/saed90nm_typ_ht.db  }
set target_library $link_library
read_file -format verilog ./const_coeff_0.vrl
link
create_clock -name CLK -period  0.001
set_input_delay  0.000 -clock CLK {R}
set_max_capacitance 65.760002 {R}
set_input_delay  0.000 -clock CLK {G}
set_max_capacitance 65.760002 {G}
set_input_delay  0.000 -clock CLK {B}
set_max_capacitance 65.760002 {B}
set_output_delay  0.000 -clock CLK {U}
set_load 4.932000 {U}
set_output_delay  0.000 -clock CLK {V}
set_load 4.932000 {V}
set_output_delay  0.000 -clock CLK {Y}
set_load 4.932000 {Y}
set_max_area 0
report_constraints -all -max_capacitance -max_transition -max_fanout
report -area -timing -path full > const_coeff_0.dc.rep
write -hier -format verilog -o const_coeff_0.dc.vrl const_coeff_0
quit
